1. Technical Field of the Invention
This invention relates generally to integrated circuits and more particularly to integrated delayed locked loops.
2. Description of Related Art
As is known, delayed locked loops (DLL) are used for clock deskewing, i.e., taking a clock signal and producing multiple phased representations of the clock signal. For example, a DLL may produce a 90 degree phase shifted representation of the clock, a 180 degree phase shifted representation of the clock, and a 270 degree phase shifted representation of the clock.
As is also known, a DLL may be implemented in a variety of ways. For instance, a fully digital DLL that produces a ninety degree phase shifted representation of a clock signal, a one hundred and eighty degree phase shifted representation of the clock, and a two hundred and seventy degree phase shifted representation of the clock includes four cascaded digital delay lines and a phase detection module. The first digital delay line receives, as its input, the input clock signal and, based on a control signal, produces the ninety degree phase shifted representation of the clock signal. The second digital delay line receives, as its input, the ninety degree phase shifted representation of the clock signal and, based on the control signal, produces the one hundred and eighty degree phase shifted representation of the clock signal. The third digital delay line receives, as its input, the one hundred and eighty degree phase shifted representation of the clock signal and, based on the control signal, produces the two hundred and seventy degree phase shifted representation of the clock signal. The fourth digital delay line receives, as its input, the two hundred and seventy degree phase shifted representation of the clock signal and, based on the control signal, produces a three hundred and sixty degree phase shifted representation of the clock signal.
The control module produces the control signal by comparing the input clock signal with the three hundred and sixty degree phase shifted representation of the clock signal. In general, the control module produces the control signal such that the three hundred and sixty degree phase shifted representation of the clock signal looks exactly like the input clock signal, but shifted by one period of the input clock cycle.
To provide an accurate and flexible DLL, each digital delay line includes a plurality of buffers that have their data transition rates controlled to produce a plurality of delayed representations of the respective input clock signal. The DLL further includes a multiplexer coupled to output one of the plurality of delayed representations of the respective input clock signal as the respective phase shifted output clock signal.
Due to the amount of circuitry required to implement each digital delay line and having four digital delay lines cascaded together, there is a finite limit as to the rate of clock signals it can deskew. For instance, if each digital delay line includes 128 taps and the DLL is implemented using 0.13 micron CMOS (Complimentary Metal Oxide Semiconductor) technology, the maximum rate of the input clock is about 500 MHz (mega Hertz).
Therefore, a need exists for a digital high speed (e.g., greater than 500 MHz) programmable delayed locked loop (DLL).